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ST
Sitronix
Features
5 x 8 dot matrix possible Low power operation support: -- 2.7 to 5.5V Wide range of LCD driver power -- 3.0 to 7.0V Support high speed serial interface Correspond to high speed MPU bus interface -- 2 MHz (when VCC = 5V) 80 x 9-bit display RAM (80 characters max.) 19840-bit character generator ROM for a total of 496 character fonts(5 x 8 dot) 64 x 8-bit character generator RAM -- 8 character fonts (5 x 8 dot)
ST7070
Dot Matrix LCD Controller/Driver
16-common x 80-segment liquid crystal display driver Programmable duty cycles -- 1/8 for one line of 5 x 8 dots with cursor -- 1/16 for two lines of 5 x 8 dots & cursor Wide range of instruction functions: Display clear, cursor home, display on/off, cursor on/off, cursor shift, display shift Automatic reset circuit that initializes the controller/driver after power on Internal oscillator with external resistors Low power consumption Bare Chip available (ST7070-XX-B)
Description
The ST7070 dot-matrix liquid crystal display controller and driver LSI displays alphanumeric, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. With high speed serial interface(3-line SPI , 4-line SPI), the external MCU can control ST7070 directly. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. The ST7070 has function partial compatibility with the HD44780, KS0066 and SED1278 that allows the user to easily replace it with an ST7070. The ST7070 character generator ROM is extended to generate 496 5x8 dot character fonts for a total of 496 different character fonts. The low power supply (2.7V to 5.5V) of the ST7070 is suitable for any portable battery-driven product requiring low power dissipation. The ST7070 LCD driver consists of 16 common signal drivers and 80 segment signal drivers which can extend display size by cascading segment driver ST7921. The maximum display size can be either 80 characters in 1-line display or 40 characters in 2-line display. A single ST7070 can display up to one 16-character line or two 16-character lines.
Product Name
ST7070-0B
Support Character
Standard code
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ST7070
ST7070 Serial Specification Revision History Version 1.0 1.1 1.2 1.2a Date 2004/4/14 Add product name 2005/1/26 2006/5/8 Add serial interface timing characteristic and change serial interface symbols Update Initial Code of serial interface Description
2006/8/31 Update the example figure of Set Display Data Length. Redraw timing figure: 6800 & serial interface. Rename timing item to avoid confuse: 6800: TC=TCYC, TDSW=TDS, TH (Write)=TDH, TDDR=TOD, TH (Read)=TOH
1.3
2008/6/16
Update AC Characteristics: 6800 (2.7V): TCYC (Write), TPW (Write), TDS, TOD 6800 (5V): TPW (Write/Read), TDS, TOD Serial (2.7V): TSCYC, TSHW/TSLW, TSAS, TSDH, TCSS, TCSH Serial (5V): TSCYC, TSHW/TSLW, TSAS, TSDH, TCSH Remove Reversion History before version 1.0.
1.4
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ST7070 Block Diagram
OSC1 OSC2 CL1 CL2 M Timing generator D
XRESET
Reset circuit Instruction register(IR)
CPG
PSB
Instruction decoder
RS RW E
Display data RAM (DDRAM) 80x9 bits
16-bit shift register
Common signal driver
COM1 to COM16
MPU interface Address counter 80-bit shift register 80-bit latch circuit Segment signal driver
SEG1 to SEG80
DB4 to DB7 Input/ output buffer
Data register (DR) LCD drive voltage selector
DB0 to DB3
Busy flag
Character generator RAM (CGRAM) 64 bytes GND
Character generator ROM (CGROM) 19840 bits
Cursor and blink controller
Parallel/serial converter and attribute circuit
Vcc V0 V1 V2 V3 V4
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ST7070 Pad Arrangement
Mark
Substrate must connect to "Vss".
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ST7070 Pad Configuration
Pad No. 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 031 032 Function RS DB[7] XRESET DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0] PSB RW E COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] X -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2585 -2445 -2315 -2195 -2085 -1975 -1865 -1755 -1645 -1535 -1425 -1315 -1208 -1102 -997 -892 -787 -682 -577 660 540 430 320 210 105 0 -105 -210 -320 -430 -540 -660 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 Y Pad No. 033 034 035 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050 051 052 053 054 055 056 057 058 059 060 061 062 063 064 Function SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] D M CL2 -472 -367 -262 -157 -52 52 157 262 367 472 577 682 787 892 997 1102 1207 1315 1425 1535 1645 1755 1865 1975 2085 2195 2315 2445 2585 2585 2585 2585 X -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -790 -660 -540 -430 Y
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Pad No. 065 066 067 068 069 070 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 096 097 Function CL1 OSC2 OSC1 VSS V4 V3 V2 V1 V0 VDD SEG[40] SEG[39] SEG[38] SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] X 2585 2585 2585 2585 2585 2585 2585 2585 2585 2585 2585 2445 2315 2195 2085 1975 1865 1755 1645 1535 1425 1315 1207 1102 997 892 787 682 577 472 367 262 157 -320 -210 -105 0 105 210 320 430 540 660 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 Y Pad No. 098 099 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 Function SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] 52 -52 -157 -262 -367 -472 -577 -682 -787 -892 -997 -1102 -1208 -1315 -1425 -1535 -1645 -1755 -1865 -1975 -2085 -2195 -2315 -2445 -2585 X 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 790 Y
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ST7070 Pin Function
Name
RS
Number
1
I/O
I
Interfaced with
MPU
Function
Select registers. 0: Write Instruction or "Read Busy Flag and Address" 1: Data write/read It is not used in 3-Line SPI interface, fix RS at low, not floating. Select read or write. 0: Write 1: Read When serial interface select ,R/W pull low, not floating. Starts data read/write. When serial interface select ,E pull height , not floating. Hardware reset pin, Low active Parallel /Serial selection. PSB: "1" Parallel , "0" Serial. Four high order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7070. DB7 can be used as a busy flag. Serial: DB7:data input pin for serial mode(SI) DB6:serial clock input for serial mode(SCL) DB5:chip select pin for serial mode(/CS) When serial interface select ,D4 pull height , not floating. 4bits mode : These pins are used during 4-bit operation. Four low order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7070. These pins are not used during 4-bit operation and serial interface , must pull height , not floating. Clock to latch serial data D sent to the Extension driver Clock to shift serial data D Switch signal for converting the liquid crystal drive waveform to AC Character pattern data corresponding to each segment signal Common signals that are not used are changed to non-selection waveform. COM9 to COM16 are non-selection waveforms at 1/8 duty factor and COM12 to COM16 are non-selection waveforms at 1/11 duty factor. Segment signals Power supply for LCD drive V0 Vss = 10 V (Max) VCC : 2.7V to 5.5V, GND: 0V When crystal oscillation is performed, a resistor must be connected externally. When the pin input is an external clock, it must be input to OSC1.
R/W E XRESET PSB
1 1 1 1
I I I I
MPU MPU MPU MPU
DB4 to DB7
4
I/O
MPU
DB0 to DB3
4
I/O
MPU
CL1 CL2 M D
1 1 1 1
O O O O
Extension driver Extension driver Extension driver Extension driver
COM1 to COM16 SEG1 to SEG80 V0 to V4 VCC , GND OSC1, OSC2
16
O
LCD
80 5 2 2
O -
LCD Power supply Power supply Oscillation resistor clock
Note: 1. V0 >= V1 >= V2 >= V3 >= V4 >= Vss must be maintained 2. Two clock options:
R=91K (Vcc=5V) R=75K (Vcc=3V)
OSC1 R
OSC2 Clock input
OSC1
OSC2
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ST7070 Function Description
System Interface This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input pin in 4-bit/8-bit bus mode.
RS R/W
L L H H L H L H
Operation
Instruction Write operation (MPU writes Instruction code into IR) Read Busy Flag(DB7) and address counter (DB6 ~ DB0) Data Write operation (MPU writes data into DR) Data Read operation (MPU reads data from DR)
Table 1. Various kinds of operations according to RS and R/W bits. Busy Flag (BF) When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High.
Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB6 ~ DB0 ports.
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Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 9-bit character codes. Its extended capacity is 80 x 9 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal. 1-line display (N = 0) (Figure 2) When there are fewer than 80 display characters, the display begins at the head position. For example, if using only the ST7070, 8 characters are displayed. See Figure 3. When the display shift operation is performed, the DDRAM address shifts. See Figure 3.
High Order bits
Low Order bits
Example: DDRAM Address 4F 1 0 0 1 1 1 1
AC AC6 AC5 AC4 AC3 AC2 AC1 AC0
Figure 1 DDRAM Address
Display Position 1 (Digit) 00 DDRAM Address
2
3
4
5
6
78
79
80
01
02
03
04
05
....................
4D 4E
4F
Figure 2 1-Line Display
Display Position DDRAM Address
1
2
3
4
5
6
7
8
00
01
02
03
04
05
06
07
For Shift Left
01
02
03
04
05
06
07
08
For Shift Right
4F
00
01
02
03
04
05
06
Figure 3 1-Line by 8-Character Display Example
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ST7070
2-line display (N = 1) (Figure 4)
Display Position
1
2
3
4
5
6
38
39
40
00 DDRAM Address 40 (hexadecimal)
01 41
02 42
03 43
04 44
05 45
.................... ....................
25 65
26 66
27 67
Figure 4 2-Line Display Case 1: When the number of display characters is less than 40 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the ST7070 is used, 16 characters 2 lines are displayed. See Figure 5. When display shift operation is performed, the DDRAM address shifts. See Figure 5.
Display
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Position 00 DDRAM Address 40
01 41
02 42
03 43
04 44
05 45
06 46
07 47
08 48
09 49
0A 4A
0B 0C 0D 0E 4B 4C 4D 4E
0F 4F
For Shift Left
01 41
02 42
03 43
04 44
05 45
06 46
07 47
08 48
09 49
0A 4A
0B 0C 0D 0E 4B 4C 4D 4E
0F 4F
10 50
For Shift Right
27 67
00 40
01 41
02 42
03 43
04 44
05 45
06 46
07 47
08 48
09 49
0A 4A
0B 0C 0D 0E 4B 4C 4D 4E
Figure 5 2-Line by 16-Character Display Example
Case 2: For a 16-character x 2-line display, See Figure 5. When display shift operation is performed, the DDRAM address shifts. See Figure 5.
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Character Generator ROM (CGROM) The character generator ROM generates 5 x 8 dot character patterns from 9-bit character codes. It can generate 496 5 x 8 dot character patterns. User-defined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written. Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM. See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area. LCD Driver Circuit LCD Driver circuit has 16 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is selected by 16 bit common register, segment data also output through segment driver from 80 bit segment latch. In case of 1-line display mode, COM1 ~ COM8 have 1/8 duty, and in 2-line mode, COM1 ~ COM16 have 1/16 duty ratio. Cursor Control Circuit It can generate the cursor in the cursor control circuit. The cursor or the blink appears in the digit at the display data RAM address set in the address counter.
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Table 4 Correspondence between Character Codes and Character Patterns (Page 1) (b8=0)
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Table 4 Correspondence between Character Codes and Character Patterns (Page 2) (b8=1)
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Character Code (DDRAM Data)
b8 b7 b6 b5 b4 b3 b2 0 0 0 0 000000 0 0 0 0 0 0 0 000000 0 0 0 b1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CGRAM Address
b0 b5 b4 b3 b2 0 0 0 0 0 0 0 0 000 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 001 1 1 1 1 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Character Patterns (CGRAM Data)
b0 b7 b6 b5 b4 0 1 1 0 0 0 1 0 --0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 1 --0 1 1 1 0 1 1 0 b3 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 b2 1 1 1 1 1 1 1 0 1 0 0 1 1 0 0 0 b1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 b0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns (CGRAM Data) Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left). 4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either character code 00H or 08H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. "-": Indicates no effect.
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ST7070 Instructions
There are four categories of instructions that: Designate ST7070 functions, such as display format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Others Instruction Table:
Instruction Code Instruction EXT = 0 or 1 Clear Display Return Home Display ON/OFF Cursor or Display Shift Function Set Read Busy flag and address Write data to RAM Read data from RAM EXT = 0 Entry Mode Set Set CGRAM address Set DDRAM address
Sets cursor move direction and specifies display shift. These operations are performed during data write and read. Set CGRAM address in address counter Set DDRAM address in address counter
0 0 0 0 0 0 0 0 0 1
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Description Time
(270KHz)
Write "20H" to DDRAM. and set DDRAM address to "00H" from AC Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. D=1:entire display on C=1:cursor on P: font table page selection Set cursor moving and display shift control bit, and the direction, without changing DDRAM data. DL: interface data is 8/4 bits N: number of line is 2/1
1.52 ms
0
0
0
0
0
0
0
0
1
x
0 us
0
0
0
0
0
0
1
D
C
P
37 us
0
0
0
0
0
1
S/C
R/L
x
x
37 us
0
0
0
0
1
DL
N
EXT
x
x
37 us
0
1
BF
1
0
D7
1
1
D7
Whether during internal operation or not can be AC6 AC5 AC4 AC3 AC2 AC1 AC0 known by reading BF. The contents of address counter can also be read. Write data into internal D6 D5 D4 D3 D2 D1 D0 RAM (DDRAM/CGRAM) Read data from internal D6 D5 D4 D3 D2 D1 D0 RAM (DDRAM/CGRAM)
0 us
37 us 37 us
0
0
0
0
0
0
0
1
I/D
S
37 us
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
37 us 37 us
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
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EXT = 1
Used internal resister only provide 1/5 bias mode . Rb[1:0]=00 External Rb1 Rb0 Resister Rb[1:0]=01~11 Internal Resistor C1com1~8 com8~1 C2com9~16 com16~9 S1 S2 S1seg1~40 seg40~1 S2seg41~80 seg80~41
L1 L0
Bias resistor select
0
0
0
0
0
0
0
1
37 us
COMSEG direction select Set display data length
0
0
0
1
0
0
C1
C2
37 us
0
0
1
L6
L5
L4
L3
L2
To specify the number of data bytes(3SPI mode)
37 us
Note: Be sure the ST7070 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7070. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction execution time.
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ST7070 Instruction Description
EXT=0 or 1 Clear Display
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). Return Home
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
0
1
x
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.
Display ON/OFF
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
1
D
C
P
Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
Alternating display Every 32 frames Cursor
P : Font table selection bit When P = "Low", it select page 1 of font table.(set DDRAM data bit-8=0) When P = "High", it select page 2 of font table(set DDRAM data bit-8=1)
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Cursor or Display Shift
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
1
S/C R/L
x
x
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed.
S/C
L L H H Function Set
R/L
L H L H
Description
Shift cursor to the left Shift cursor to the right Shift display to the left. Cursor follows the display shift
AC Value
AC=AC-1 AC=AC+1 AC=AC
Shift display to the right. Cursor follows the display shift AC=AC
RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
1
DL
N
EXT
x
x
DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. N : Display line number control bit When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. EXT : Select basic or extended instruction set When EXT="L" the commands `Entry Mode Set' , `Set CGRAM address' and `Set DDRAM address' can be performed , when EXT="H" the commands `Bias resistor select' , `COMSEG direction select' and `Set display data length' can be performed. Other command can be executed in both cases. When EXT="L" : disable extension instruction When EXT="H" : enable extension instruction
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Read Busy Flag and Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
1
BF
AC6 AC5 AC4 AC3 AC2 AC1 AC0
When BF = "High", indicates that the internal operation is being processed.So during this time the next instruction cannot be accepted. The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. Write Data to CGRAM or DDRAM
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
1
0
D7 D6 D5 D4 D3 D2 D1 D0
Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC direction to RAM. DDRAM data bit-8 is come from "P"(Display on/off instruction) register setting After write operation, the address is automatically increased/decreased by 1, according to the entry mode.
Read Data from CGRAM or DDRAM
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
1
1
D7 D6 D5 D4 D3 D2 D1 D0
Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction.
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ST7070
EXT=0 Entry Mode Set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
1
I/D
S
Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when read from or write to CGRAM. S: Shift of entire display When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1" : shift left, I/D = "0" : shift right).
S
H H
I/D
H L
Description
Shift the display to the left Shift the display to the right
Set CGRAM Address
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Code
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. Set DDRAM Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H".
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ST7070
EXT=1 Bias resistor select
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
1
Rb1 Rb0
Set internal bias resistor value.
Rb1
L L H H
Rb0
L H L H
Description
External bias resistor select. Build-in resistor select (R=2.2K). Build-in resistor select (R=6.8K).
Build-in resistor select (R=9.0K).
COMSEG direction select
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
1
0
0
C1
C2
S1
S2
The SEG and COM output in ST7070 all have bi-direction control by the register. COM OUTPUT : COM output C1 0 1 COM1 COM1 COM8 Common Address Common Address COM8 COM8 COM1
COM output C2 0 1 SEG OUTPUT : SEG output S1 0 1 SEG1 SEG1 SEG40 Segment Address Segment Address SEG40 SEG40 SEG1 COM9 COM9 COM16 Common Address Common Address COM16 COM16 COM9
SEG output S2 0 1 SEG41 SEG41 SEG80 Segment Address Segment Address SEG80 SEG80 SEG41
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ST7070
Set display data length
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
1
L6
L5
L4
L3
L2
L1
L0
L6 0 0 ... 1 1
L5 0 0 ... 0 0
L4 0 0 ... 0 0
L3 0 0 ... 1 1
L2 0 0 ... 1 1
L1 0 0 ... 1 1
L0 0 1 .... 0 1
Data length 1 2 ... 79 80
Only in 3line-SPI interface will use the register to set the number of display data(Max=4F). To write data to DDRAM , send Data Direction Command in 3-pin SPI . Data is latched at the rising edge of SCLK . And the DDRAM column address pointer will be increased by one automatically.
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ST7070 Reset Function
Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the ST7070 when the power is turned on or hardware reset pin has low. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 40 ms after VCC rises to 4.5 V. 1. Display clear 2. Function set: DL = 1; 8-bit interface data N = 1; 2-line display EXT=0;disable extension instruction. 3. Display on/off control: D = 0; Display off C = 0; Cursor off P = 0; Page 1 of font table(DDRAM data b8=0) 4. Entry mode set: I/D = 1; Increment by 1 S = 0; No shift 5. Bias resistor select: Rb1=0;Rb2=0 select external bias resistor. 6. COMSEG direction select: C1=0;C2=0;S1=0;S2=0 not reverse. Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the ST7070. For such a case, initialization must be performed by the MPU as explain by the following figure.
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ST7070 Initializing by Instruction
8-bit Interface (fosc=270KHz)
POWER ON
Wait time >40mS After Vcc >4.5V
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N X X X
BF cannot be checked before this instruction.
Wait time >37uS
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N X X X
BF cannot be checked before this instruction.
Wait time >37uS
Display ON/OFF control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C P
Wait time >37uS
Display clear
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1
Wait time >1.52mS
Entry mode set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D S
Initialization end
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ST7070
Initial Program Code Example For 8051 MPU(8 Bit Interface): ;--------------------------------------------------------------------------------INITIAL_START: CALL DELAY40mS MOV CALL CALL MOV CALL CALL MOV CALL CALL MOV CALL CALL A,#38H ;FUNCTION SET WRINS_NOCHK ;8 bit,N=1,5*7dot DELAY37uS A,#38H ;FUNCTION SET WRINS_NOCHK ;8 bit,N=1,5*7dot DELAY37uS A,#0FH WRINS_CHK DELAY37uS A,#01H WRINS_CHK DELAY1.52mS ;DISPLAY ON
;CLEAR DISPLAY
MOV A,#06H ;ENTRY MODE SET CALL WRINS_CHK ;CURSOR MOVES TO RIGHT CALL DELAY37uS ;--------------------------------------------------------------------------------MAIN_START: XXXX XXXX XXXX XXXX . . . . ;--------------------------------------------------------------------------------WRINS_CHK: CALL CHK_BUSY WRINS_NOCHK: CLR RS ;EX:Port 3.0 CLR RW ;EX:Port 3.1 SETB E ;EX:Port 3.2 MOV P1,A ;EX:Port 1=Data Bus CLR E MOV P1,#FFH ;For Check Busy Flag RET ;--------------------------------------------------------------------------------CHK_BUSY: ;Check Busy Flag CLR RS SETB RW SETB E JB P1.7,$ CLR E RET
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ST7070
4-bit Interface (fosc=270KHz)
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ST7070
Initial Program Code Example For 8051 MPU(4 Bit Interface):
;------------------------------------------------------------------INITIAL_START: CALL DELAY40mS MOV CALL CALL MOV CALL CALL A,#38H WRINS_ONCE DELAY2mS A,#38H WRINS_ONCE DELAY37uS ;FUNCTION SET ;8 bit,N=1,5*7dot
;FUNCTION SET ;8 bit,N=1,5*7dot
MOV CALL CALL MOV CALL CALL MOV CALL CALL MOV CALL CALL MOV CALL CALL
A,#38H WRINS_ONCE DELAY37uS
;FUNCTION SET ;8 bit,N=1,5*7dot
A,#28H ;FUNCTION SET WRINS_NOCHK ;4 bit,N=1,5*7dot DELAY37uS A,#28H ;FUNCTION SET WRINS_NOCHK ;4 bit,N=1,5*7dot DELAY37uS A,#0FH WRINS_CHK DELAY37uS A,#01H WRINS_CHK DELAY1.52mS ;DISPLAY ON
;CLEAR DISPLAY
MOV A,#06H ;ENTRY MODE SET CALL WRINS_CHK CALL DELAY37uS ;------------------------------------------------------------------MAIN_START: XXXX XXXX XXXX XXXX . . . . . . . . .
;------------------------------------------------------------------WRINS_CHK: CALL CHK_BUSY WRINS_NOCHK: PUSH A ANL A,#F0H CLR RS ;EX:Port 3.0 CLR RW ;EX:Port 3.1 SETB E ;EX:Port 3.2 MOV P1,A ;EX:Port1=Data Bus CLR E POP A SWAP A WRINS_ONCE: ANL A,#F0H CLR RS CLR RW SETB E MOV P1,A CLR E MOV P1,#FFH ;For Check Bus Flag RET ;------------------------------------------------------------------CHK_BUSY: ;Check Busy Flag PUSH A MOV P1,#FFH $1 CLR RS SETB RW SETB E MOV A,P1 CLR E MOV P1,#FFH CLR RS SETB RW SETB E NOP CLR E JB A.7,$1 POP A RET
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ST7070
Serial Interface (fosc=270KHz)
POWER ON
Wait time >40mS After Vcc >4.5V
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N X X X
BF cannot be checked before this instruction.
Wait time >37uS
Display ON/OFF control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C P
Wait time >37uS
Display clear
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1
Wait time >1.52mS
Entry mode set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D S
Initialization end
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ST7070 Interfacing to the MPU
The ST7070 can send data in either two 4-bit operations or one 8-bit operation or serial operation, thus allowing interfacing with 4- or 8-bit or serial MPU.
For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the ST7070 and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data.
Example of busy flag check timing sequence
RS
R/W
E
Internal operation
Functioning
DB7
IR7
IR3
AC 3 Busy flag check
Not AC Busy 3 Busy flag check
IR7
IR3
Instruction write
Instruction write
Intel 8051 interface
COM1 to COM16 P1.0 to P1.3 4 DB4 to DB7
16
P3.0 P3.1 P3.2 Intel 8051 Serial
RS R/W E
SEG1 to SEG80
80
ST7070
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ST7070
For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
Example of busy flag check timing sequence
RS
R/W
E
Internal operation
Functioning
DB7
Data Instruction write
Busy Busy flag check
Busy Busy flag check
Not Busy Busy flag check
Data Instruction write
Intel 8051 interface
COM1 to COM16 P1.0 to P1.7 8 DB0 to DB7
16
P3.0 P3.1 P3.2 Intel 8051 Serial
RS R/W E
SEG1 to SEG80
80
ST7070
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ST7070
For serial interface data, bus lines (DB5 to DB7) are used. 4-Pin SPI
Example of timing sequence
CSB
SI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
RS
Intel 8051 interface(Serial)
COM1 to COM16 P1.5to P1.7 3 SI , SCL , /CS
16
P3.0
RS SEG1 to SEG80 80
Intel 8051 Serial
ST7070
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ST7070
For serial interface data, bus lines (DB5 to DB7) are used. 3-Pin SPI
Example of timing sequence
/CB SI SCL
set command number of data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 display data length DB7 DB6 DB5 DB4 DB3
set data
Intel 8051 interface(Serial)
COM1 to COM16 P1.5to P1.7 3 SI , SCL , /CS
16
SEG1 to SEG80 Intel 8051 Serial ST7070
80
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ST7070 Supply Voltage for LCD Drive
There are different voltages that supply to ST7070's pin (V0 - V4) to obtain LCD drive waveform. We could use the register command (Ra1,Ra0) to set up the Internal or External Bias Resister. The relations of the bias, duty factor and supply voltages are shown as below. External Bias Resistor could set up to 1/4 bias and 1/5 bias, but Internal Bias Resistor only could set up to 1/5 bias.
External Resistor Supply Voltage Bias Resistor Select V0 V1 V2 V3 V4 1/8
Duty Factor 1/8,1/16 Bias 1/4 Ra1=0,Ra0=0 VLCD 3/4VLCD 1/2VLCD 1/2VLCD 1/4VLCD 1/5 Ra1=0,Ra0=0 VLCD 4/5VLCD 3/5VLCD 2/5VLCD 1/5VLCD
+5V
+5V
VR V0 R V1 V2 V3 V4 R 1/4 bias (1/8 duty cycle) 1/5 bias (1/16 duty cycle) R VLCD R V1 V0
VR R R V2 V3 V4 R R R VLCD
Vss
Vss
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ST7070
Internal Resistor Supply Voltage Bias Resistor Select Internal Resistor V0 V1 V2 V3 V4 1/5 Ra1=0,Ra0=1 R=2.2K VLCD 4/5VLCD 3/5VLCD 2/5VLCD 1/5VLCD Duty Factor 1/8 , 1/16 Bias 1/5 Ra1=1,Ra0=0 R=6.8K VLCD 4/5VLCD 3/5VLCD 2/5VLCD 1/5VLCD 1/5 Ra1=1,Ra0=1 R=9.0K VLCD 4/5VLCD 3/5VLCD 2/5VLCD 1/5VLCD
+5V Ra1=0,Ra0=1 VR V0 R V1 R V2 V3 V4 VSS 1/5 bias R=2.2K (1/8,1/16 duty cycle) GND +5V Ra1=1,Ra0=1 VR V0 R V1 R V2 V3 V4 VSS 1/5 bias R=9.0K (1/8,1/16 duty cycle)
V1.4
+5V Ra1=1,Ra0=0 VR V0 R V1 R V2 VLCD V3 V4 VSS 1/5 bias R=6.8K (1/8,1/16 duty cycle) GND R R R VLCD
R R R
R R R
VLCD
GND
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ST7070 Timing Characteristics
Parallel Interface Write/Read by MPU
Writing data from MPU to ST7070 (Serial)
CSB
tCSS tSAS
tCSH tSAH
RS
tSCYC
SCL
tSLW tf tSDS
tSHW tr tSDH
SI
VIH VIL
First bit
Last bit
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ST7070
Interface Timing with External Driver
tct VOH2 CL1 tCWH tCWH VOL2
CL2 tCST tCWL tct D tDH tSU M tDM
Internal Power Supply Reset
2.7V/4.5V
0.2V
0.2V
0.2V
trcc 0.1mStrcc80mS
tOFF tOFF1mS
Notes: tOFF compensates for the power oscillation period caused by momentary power supply oscillations. Specified at 4.5V for 5V operation,and at 2.7V for 3V operation. For if 4.5V is not reached during 5V operation,teh internal reset circuit will not operate normally.
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ST7070 AC Characteristics
In 6800 interface (TA = 25 VCC = 2.7V ) C, Symbol Characteristics
fOSC OSC Frequency
Test Condition
Internal Clock Operation R = 75K External Clock Operation
Min. Typ. Max.
190 270 350
Unit
KHz
fEX
External Frequency Duty Cycle
-
125 45 -
270 50 -
410 55 0.2
KHz % s
Tr,Tf
Rise/Fall Time
Write Mode (Writing data from MPU to ST7070) TCYC TPW Tr,Tf TAS TAH TDS TDH Enable Cycle Time Pin E (except clear display) 60 30 0 10 30 10 25 us ns ns ns ns ns ns
Enable Pulse Width Pin E Enable Rise/Fall Time Pin E Address Setup Time Pins: RS,RW Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW Pins: DB0 - DB7 Pins: DB0 - DB7
Read Mode (Reading Data from ST7070 to MPU) TCYC TPW Tr,Tf TAS TAH TOD TOH Enable Cycle Time Pin E 1200 480 0 10 10 25 420 ns ns ns ns ns ns ns
Enable Pulse Width Pin E Enable Rise/Fall Time Pin E Address Setup Time Pins: RS,RW Address Hold Time Output Delay Time Output Hold Time Pins: RS,RW Pins: DB0 - DB7 Pins: DB0 - DB7
Interface Mode with LCD Driver(ST7921) TCWH TCWL TCST TSU TDH TDM Clock Pulse with High Pins: CL1, CL2 Clock Pulse with Low Pins: CL1, CL2 Clock Setup Time Data Setup Time Data Hold Time M Delay Time Pins: CL1, CL2 Pin: D Pin: D Pin: M 800 800 500 300 300 0 2000 ns ns ns ns ns ns
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ST7070 AC Characteristics
In 6800 interface (TA = 25 VCC = 5V) C, Symbol Characteristics
fOSC OSC Frequency
Test Condition
Internal Clock Operation R = 91K External Clock Operation
Min. Typ. Max.
190 270 350
Unit
KHz
fEX
External Frequency Duty Cycle
-
125 45 -
270 50 -
410 55 0.2
KHz % s
Tr,Tf
Rise/Fall Time
Write Mode (Writing data from MPU to ST7070) TCYC TPW Tr,Tf TAS TAH TDS TDH Enable Cycle Time Pin E (except clear display) 40 20 0 10 20 10 25 us ns ns ns ns ns ns
Enable Pulse Width Pin E Enable Rise/Fall Time Pin E Address Setup Time Pins: RS,RW,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: DB0 - DB7 Pins: DB0 - DB7
Read Mode (Reading Data from ST7070 to MPU) TCYC TPW Tr,Tf TAS TAH TOD TOH Enable Cycle Time Pin E 1200 430 0 10 10 25 390 ns ns ns ns ns ns ns
Enable Pulse Width Pin E Enable Rise/Fall Time Pin E Address Setup Time Pins: RS,RW,E Address Hold Time Output Delay Time Output Hold Time Pins: RS,RW,E Pins: DB0 - DB7 Pins: DB0 - DB7
Interface Mode with LCD Driver(ST7921) TCWH TCWL TCST TSU TDH TDM Clock Pulse with High Pins: CL1, CL2 Clock Pulse with Low Pins: CL1, CL2 Clock Setup Time Data Setup Time Data Hold Time M Delay Time Pins: CL1, CL2 Pin: D Pin: D Pin: M 800 800 500 300 300 0 2000 ns ns ns ns ns ns
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ST7070 AC Characteristics
In Serial interface (TA = 25 VCC = 2.7V ) C, Symbol Characteristics
fOSC OSC Frequency
Test Condition
Internal Clock Operation R = 75K External Clock Operation
Min. Typ. Max.
190 270 350
Unit
KHz
fEX
External Frequency Duty Cycle
-
125 45 -
270 50 -
410 55 0.2
KHz % s
Tr,Tf
Rise/Fall Time
Write Mode (Writing data from MPU to ST7070) TSCYC TSHW,SLW Tr,Tf TSAS TSAH TSDS TSDH TCSS TCSH SCL Cycle Time SCL Pulse Width SCL Rise/Fall Time SCL SCL SCL 2480 1190 75 10 10 75 75 250 25 ns ns ns ns ns ns ns ns ns
Address Setup Time RS Address Hold Time Data Setup Time Data Hold Time CS-SCL Time CS-SCL Time RS SI SI CS CS
Interface Mode with LCD Driver(ST7921) TCWH TCWL TCST TSU TDH TDM Clock Pulse with High Pins: CL1, CL2 Clock Pulse with Low Pins: CL1, CL2 Clock Setup Time Data Setup Time Data Hold Time M Delay Time Pins: CL1, CL2 Pin: D Pin: D Pin: M 800 800 500 300 300 0 2000 ns ns ns ns ns ns
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ST7070 AC Characteristics
In Serial Interface (TA = 25 VCC = 5V) C, Symbol Characteristics
fOSC OSC Frequency
Test Condition
Internal Clock Operation R = 91K External Clock Operation
Min. Typ. Max.
190 270 350
Unit
KHz
fEX
External Frequency Duty Cycle
-
125 45 -
270 50 -
410 55 0.2
KHz % s
Tr,Tf
Rise/Fall Time
Write Mode (Writing data from MPU to ST7070) TSCYC TSHW,SLW Tr,Tf TSAS TSAH TSDS TSDH TCSS TCSH SCL Cycle Time SCL Pulse Width SCL Rise/Fall Time SCL SCL SCL 2010 1010 60 10 10 60 60 160 25 ns ns ns ns ns ns ns ns ns
Address Setup Time RS Address Hold Time Data Setup Time Data Hold Time CS-SCL Time CS-SCL Time RS SI SI CS CS
Interface Mode with LCD Driver(ST7921) TCWH TCWL TCST TSU TDH TDM Clock Pulse with High Pins: CL1, CL2 Clock Pulse with Low Pins: CL1, CL2 Clock Setup Time Data Setup Time Data Hold Time M Delay Time Pins: CL1, CL2 Pin: D Pin: D Pin: M 800 800 500 300 300 0 2000 ns ns ns ns ns ns
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ST7070 Absolute Maximum Ratings
Characteristics
Power Supply Voltage LCD Driver Voltage Input Voltage Operating Temperature Storage Temperature
Symbol
VCC VLCD VIN TA TSTO
Value
-0.3 to +5.5 Vss+7.0 to Vss-0.3 -0.3 to VCC+0.3 -40C to + 90C -55C to + 125C
DC Characteristics
( TA = 25 VCC = 2.7 V - 4.5 V ) C, Test Condition Symbol Characteristics
VCC VLCD ICC Operating Voltage LCD Voltage Power Supply Current Input High Voltage (Except OSC1) Input Low Voltage (Except OSC1) Input High Voltage (OSC1) Input Low Voltage (OSC1) Output High Voltage (DB0 - DB7) Output Low Voltage (DB0 - DB7) Output High Voltage (Except DB0 - DB7) Output Low Voltage (Except DB0 - DB7) Common Resistance Segment Resistance Input Leakage Current Pull Up MOS Current V0 - Vss fOSC = 270KHz VCC=3.0V -
Min. Typ. Max.
2.7 3.0 0.1 4.5 7.0 0.25
Unit
V V mA
VIH1
0.7Vcc
-
VCC
V
VIL1
-
- 0.3
-
0.6
V
VIH2
-
0.7Vcc
-
VCC
V
VIL2
-
0.75 Vcc -
-
0.2Vcc
V
VOH1
IOH = -0.1mA
-
-
V
VOL1
IOL = 0.1mA
-
0.2Vcc
V
VOH2
IOH = -0.04mA
0.8VCC
-
VCC
V
VOL2 RCOM RSEG ILEAK IPUP
IOL = 0.04mA VLCD = 4V, Id = 0.05mA VLCD = 4V, Id = 0.05mA VIN = 0V to VCC VCC = 3V
-1 10
2 2 60
0.2VCC 20 30 1 120
V K K A A
NOTE : External bias resistor select , so Idd doesn't include the follower current.
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ST7070 DC Characteristics
( TA = 25C, VCC = 4.5 V - 5.5 V ) Symbol Characteristics
VCC VLCD ICC Operating Voltage LCD Voltage Power Supply Current Input High Voltage (Except OSC1) Input Low Voltage (Except OSC1) Input High Voltage (OSC1) Input Low Voltage (OSC1) Output High Voltage (DB0 - DB7) Output Low Voltage (DB0 - DB7) Output High Voltage (Except DB0 - DB7) Output Low Voltage (Except DB0 - DB7) Common Resistance Segment Resistance Input Leakage Current Pull Up MOS Current
Test Condition
V0 - Vss fOSC = 270KHz VCC=5.0V -
Min. Typ. Max.
4.5 3.0 0.2 5.5 7.0 0.5
Unit
V V mA
VIH1
2.5
-
VCC
V
VIL1
-
-0.3
-
0.6
V
VIH2
-
VCC-1
-
VCC
V
VIL2
-
-
-
1.0
V
VOH1
IOH = -0.1mA
3.9
-
VCC
V
VOL1
IOL = 0.1mA
-
-
0.4
V
VOH2
IOH = -0.04mA
0.9VCC
-
VCC
V
VOL2 RCOM RSEG ILEAK IPUP
IOL = 0.04mA VLCD = 4V, Id = 0.05mA VLCD = 4V, Id = 0.05mA VIN = 0V to VCC VCC = 5V
-1 90
2 2 200
0.1VCC 20 30 1 330
V K K A A
NOTE : External bias resistor select , so Idd doesn't include the follower current.
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ST7070 LCD Frame Frequency
Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us, 1/16 duty; 1/5 bias,1 frame = 3.7us x 200 x 16 = 11840us=11.8ms(84.7Hz)
200 clocks 1 2 3 4 16 1 2 3 4 16 1 2 3 4 16
V0 V1 V2 COM1 V3 V4 Vss
V0 V1 V2 COM2 V3 V4 Vss
V0 V1 V2 COM16 V3 V4 Vss
V0 V1 V2 SEGx off V3 V4 Vss
V0 V1 V2 SEGx on V3 V4 Vss 1 frame
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ST7070
Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us, 1/8 duty; 1/4 bias,1 frame = 3.7us x 400 x 8 = 11840us=11.8ms (84.7Hz)
400 clocks 1 2 3 4 8 1 2 3 4 8 1 2 3 4 8
V0 V1 COM1 V2 V3 V4 Vss
V0 V1 COM2 V2 V3 V4 Vss
V0 V1 COM8 V2 V3 V4 Vss
V0 V1 SEGx off V2 V3 V4 Vss
V0 V1 SEGx on V2 V3 V4 Vss 1 frame
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ST7070 I/O Pad Configuration
VCC VCC PSB PMOS PMOS PSB PMOS VCC
VCC
NMOS
NMOS NMOS
PSB=1==>E(Floating) PSB=0==>E(Pull up)
PSB=1==>R/W(With Pull up) PSB=0==>R/W(With Pull down)
VCC PSB PMOS
VCC
PMOS
NMOS PSB=1==>RS(With Pull up) PSB=0==>RS(Floating)
VCC PMOS
Output PAD:CL1,CL2,M,D
NMOS
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ST7070
VCC PMOS
VCC PMOS
VCC Enable PMOS
NMOS
Data NMOS I/O PAD:DB4-DB0 PSB=1==> Pull up PSB=0==>Pull up
VCC PSB PMOS
VCC PMOS
VCC Enable PMOS
NMOS
Data NMOS I/O PAD:DB7-DB5 PSB=1==> Pull up PSB=0==>Floating
V1.4
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ST7070 LCD and ST7070 Connection
1. 5x8 dots, 16 characters x 1 line (1/4 bias, 1/8 duty)
ST7070
COM1 . . . . . . . . COM8 SEG1 . . . . . SEG80 LCD Panel: 16 Characters x 1 line
2. 5x8 dots, 16 characters x 2 line (1/5 bias, 1/16 duty)
COM1 . . . . . . . . COM8 COM9 . . . . . . . . COM16 SEG1 . . . . . . . . . . SEG80 LCD Panel: 16 Characters x 2 line
V1.4
ST7070
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ST7070
3. 5x8 dots, 32 characters x 1 line (1/5 bias, 1/16 duty)
COM1 . . . . . . . . COM8 SEG1 . . . . . . SEG80 COM9 . . . . . . . . COM16
ST7070
LCD Panel: 32 Characters x 1 line
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Dot Matrix LCD Panel
2 (Line) X 40 ( Characters ) 5X8 dots/character
Com 1-16 D DL1 VCC SHL1 SHL2 VSS V0 V2 V3
Seg 1-80
Seg 1~96
DR2 DL2 DR1
DL1 VCC
Seg 1~24
DR2
DL2
DR1
ST7921
CL1 CL2 M
SHL1 SHL2 VSS V0 V2
ST7921
CL1
CL2
M
V3
ST7070
VCC GND CL2 CL1 M V0 V1 V2 V3 RS/RW/E/DB0-DB7 V4
Application Circuit
VR Vcc(+5V)
Resistor
Resistor
Resistor
Resistor
Resistor
ST7070
VSS To MPU
VR=10K~30Kohm
V1.4
Note:Resistor=2.2K~10K ohm
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ST7070 THE MPU INTERFACE
The ST7070 Series can be connected to 6800 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7070 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7070 Series chips . When this is done , the chip select signal can be used to select the individual Ics to access. (1) 6800 8 bits Series MPUs
VDD
VCC RS RS
VDD PSB V0
VLCD
R R
D0 to D7
D0 to D7 R/W E V3 /RES V4
MPU
R/W E /RES
ST7070
V1 R V2 R R R VSS
When use external bias resistor must connect
GND
GND
VSS
(2) 6800 4 bits Series MPUs
VDD
VCC D0 to D3 RS D4 to D7 RS
VDD PSB V0
VLCD
R R
D4 to D7 R/W E V3 /RES V4
MPU
R/W E /RES
ST7070
V1 R V2 R R R VSS
When use external bias resistor must connect
GND
GND
VSS
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ST7070
(3) Using the Serial Interface--For 4 SPI
VDD
VCC RS D7(SI) D6(SCL) D0 to D5 RS D7(SI) D6(SCL) D5(CS) R/W E GND /RES /RES
VDD PSB V0
VLCD
R R
MPU
D5(CS)
ST7070
V1 R V2 V3 V4 GND R R R VSS
When use external bias resistor must connect
VSS
(4) Using the Serial Interface--For 3 SPI
VDD
VCC D0 to D5 RS D7(SI) D6(SCL) D7(SI) D6(SCL) D5(CS) R/W E GND /RES /RES
VDD PSB V0
VLCD
R R
MPU
D5(CS)
ST7070
V1 R V2 V3 V4 GND R R R VSS
When use external bias resistor must connect
VSS
V1.4
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